multi vector interrupts

[jpc]

one of the interesting features of the 18FxxK42 is the multi vector interrupt so this was the first i looked into, for some reason the compiler does not report any generated code once the IVT enabled setting is active, assembly listing seems to be correct but no .DBG file is generated , software debugging hence is not possible.
The C compiler seems to behave better , it does generate all files required to enter software debugger

[janni]

I've also stumbled on a case when linker gets confused and doesn't produce final code even though compilation succeeded. This happens when there's a uses clause (include clause in mB) containing unit (module) that wasn't added to Project Manager. This problem shows up only with vectored interrupts chosen.

Could you post your code if it's another case?

[jpc]

my first test is very simple to reproduce, take for example led blink example and change to 18F47K42, when IVT is enabled it compiles but no longer reports RAM/ROM usage and does not generate DBG file, behaviour in MikroBasic seems similar.
I also see a hint that i do not understand : Hint: interrupt handler (test at 0x0000) LedBlinking.mpas where test is the name of my interrupt , why adress 0x0000 ?

[janni]

my first test is very simple to reproduce, take for example led blink example and change to 18F47K42, when IVT is enabled it compiles but no longer reports RAM/ROM usage and does not generate DBG file, behaviour in MikroBasic seems similar.

Indeed, but when I added Delays library to Project Manager it compiled and linked. Same effect when any library from Library Manager is checked. Apparently linker requires company .

I also see a hint that i do not understand : Hint: interrupt handler (test at 0x0000) LedBlinking.mpas where test is the name of my interrupt , why adress 0x0000 ?

I don't see this message when linker fails or when there's no ISR. When linker works, only active ISR vectors are listed. Did you declare some ISR without specifying it's vector?

Single ISR should contain vector (iv) and priority level (ilevel) declaration, like

Code: Select all

procedure ISR_TMR2; iv IVT_TMR2; ilevel 1; ics ICS_OFF;

[jpc]

Janni,

that helps, indeed after adding any library to the project it links ok, what is however the importance of the priority level in the declaration of the ISR ?I suppose the priority level is determined by the individual IP bit's or is this significant for the linker?
I also notice that in the software debugger, selecting the available interrupts list for only used does not make any difference, all vectors are listed

[janni]

that helps, indeed after adding any library to the project it links ok, what is however the importance of the priority level in the declaration of the ISR ?I suppose the priority level is determined by the individual IP bit's or is this significant for the linker?

The priority level is for the linker only as linker does not check IPR registers' setting. But using declaration different than ilevel 1 is at the moment disadvantageous as with lower priority setting compiler unnecessarily tries to save basic registers and switches off hardware context saving. (BTW, I mistakenly wrote ilevel 0 in my example, which, as the default, doesn't have to be added - it's corrected now.)

I also notice that in the software debugger, selecting the available interrupts list for only used does not make any difference, all vectors are listed

Yeah, like with the obligatory library inclusion, it's one of many unpolished details...

Please take a look at mC beta testing forum - most of quirks are being reported there.