#3
Post
by rrid » 10 Jan 2018 15:41
Hi,
i use PIC32MX695F512L and PIC32MX440F512H
it seems that , from Library:
void UARTx_Init_Advanced(unsigned long baud_rate, unsigned long freq_Khz, unsigned short high_low, unsigned short parity, unsigned short stop_bits);
work with SYS_CLK, not PB_CLK (since MikroC Pro PIC32 version 4.0.0)
SYS_CLK = 20000
PB_CLK = 10000
two ways:
1.
#define PB_CLK 10000 // peripheral = MCU_CLK / 2
UART2_Init_Advanced(115200, PB_CLK, _UART_HIGH_SPEED, _UART_8BIT_NOPARITY, _UART_ONE_STOPBIT);
which gives me this real baudrate 230400 bps
2.
if ((PBDIV1_bit == 1) && (PBDIV0_bit == 1)) pb_divisor = 8;
else if ((PBDIV1_bit == 1) && (PBDIV0_bit == 0)) pb_divisor = 4;
else if ((PBDIV1_bit == 0) && (PBDIV0_bit == 1)) pb_divisor = 2;
else pb_divisor = 1;
periph_clock = Get_Fosc_kHz()/pb_divisor; // 20000 / 2 = 10000
UART2_Init_Advanced(115200, periph_clock, _UART_HIGH_SPEED, _UART_8BIT_NOPARITY, _UART_ONE_STOPBIT);
which gives me this real baudrate 230400 bps
I have to set: 20000 for "PB_CLK":
UART2_Init_Advanced(115200, 20000, _UART_HIGH_SPEED, _UART_8BIT_NOPARITY, _UART_ONE_STOPBIT); // TEST
which gives me the expected baudrate !
I tested this with different baudrates, with the same erroneous behaviors.
I checked the configuration by reading the chips:
1FC02FF0 DEVCFG3 0 USERID
1FC02FF4 DEVCFG2 20151 FPLLIDIV DIV_2 PLL Input Divider 2x Divider
FPLLMUL MUL_20 PLL Multiplier 20x Multiplier
UPLLIDIV DIV_2 USB PLL Input Divider 2x Divider
UPLLEN ON USB PLL Enable Enabled
FPLLODIV DIV_4 System PLL Output Clock Divider PLL Divide by 4
1FC02FF8 DEVCFG1 DD183 FNOSC PRIPLL Oscillator Selection Bits Primary Osc w/PLL (XT+,HS+,EC+PLL)
FSOSCEN OFF Secondary Oscillator Enable Disabled
IESO ON Internal/External Switch Over Enabled
POSCMOD XT Primary Oscillator Configuration XT osc mode
OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled
FPBDIV DIV_2 Peripheral Clock Divisor Pb_Clk is Sys_Clk/2
FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disable, FSCM Disabled
WDTPS PS8192 Watchdog Timer Postscaler 1:8192
FWDTEN OFF Watchdog Timer Enable WDT Disabled (SWDTEN Bit Controls)
1FC02FFC DEVCFG0 110FF00B DEBUG OFF Background Debugger Enable Debugger is disabled
ICESEL ICS_PGx2 ICE/ICD Comm Channel Select ICE EMUC2/EMUD2 pins shared with PGC2/PGD2
PWP OFF Program Flash Write Protect Disable
BWP OFF Boot Flash Write Protect bit Protection Disabled
CP OFF Code Protect Protection Disabled
Obviously if "Pb_Clk is Sys_Clk/1", the problem does not appear.
Please, can you check if there's been a change in the library?
