Question about subroutine exit and stackpointer

[Dany]

Hi, I discovered that the restoration instruction of the stackpointer is placed AFTER the return instruction (see code below).

Code: Select all

_Test2:
;SubRoutines.mpas, 11 :: 		begin
0x9D000000	0x27BDFFB0  ADDIU	SP, SP, -80 ; <---- stackpointer changed to hold local variables
;SubRoutines.mpas, 13 :: 		Dw[0] := DW[0] shl 1;
0x9D000004	0x8FA20000  LW	R2, 0(SP)
0x9D000008	0x00021040  SLL	R2, R2, 1
0x9D00000C	0xAFA20000  SW	R2, 0(SP)
;SubRoutines.mpas, 14 :: 		R23 := Dw[0];
0x9D000010	0x8FB70000  LW	R23, 0(SP)
;SubRoutines.mpas, 15 :: 		end;
L_end_Test2:
0x9D000014	0x03E00008  JR	RA;             <----- return instruction
0x9D000018	0x27BD0050  ADDIU	SP, SP, 80;  <---- restoration of the stackointer
; end of _Test2

The source code is:

Code: Select all

procedure Test2;
var Dw: array[20] of Dword;
begin
  Dw[0] := DW[0] shl 1;
  R23 := Dw[0];
end;

Can someone explain this please? My question is: how does it come that the instruction after the return instruction (JR) is executed? I would think it is never reached...
I have read about the "branch delay", which is the instruction following the branch instruction, and about prefetch, but I can not really connect these two features to the item that I've seen.

Thanks in advance!

[janni]

That's how MIPS32 architecture works. If you look up the jump instruction in MIPS32™ Architecture For Programmers you'll see in its description:

Jump to the effective target address in GPR rs. Execute the instruction following the jump, in the branch delay slot,
before jumping.

As processor already has the instruction and there's time to execute it, this architecture designers decided it would be a waste not to do it.

[Dany]

That's how MIPS32 architecture works. If you look up the jump instruction in MIPS32™ Architecture For Programmers you'll see in its description:

Jump to the effective target address in GPR rs. Execute the instruction following the jump, in the branch delay slot,
before jumping.

As processor already has the instruction and there's time to execute it, this architecture designers decided it would be a waste not to do it.

Thanks Janni. So it was the branch delay slot instruction after all... Thanks for pointing me to the document, I did not had that one yet.

But admit: it looks odd in the code...

[janni]

But admit: it looks odd in the code...

So it does...