Shadow Register Sets and Interrupts priorities on PIC32MZ

[HiEveryone]

Hi,

In the PIC32MX there is only one Shadow Register Set that can be assigned to one interrupt level and this is done via the DEVCFG3 configuration register.

However the PIC32MZ has seven (7) Shadow Register Set and each interrupt priority can have its own Shadow Register Set via the PRISS register.

I tried a simple example but the compiler still refuses it.
Here the code snippet.

Code: Select all

program Test_interrupt
sub procedure Timer1Int() iv IVT_TIMER_1 ilevel 7 ics ICS_SRS
end sub

sub procedure Timer2Int() iv IVT_TIMER_2 ilevel 6 ics ICS_SRS
end sub

main:
  INTCON.MVEC = 1
  PRISS = %01110110010101000011001000010000
end.

The compiler throughs a "Interrupt handler priority does not match SRS priority level"
Why would the compiler complain about that? Isn't the PRISS register configured correctly?

And in the project properties there is no way to set that, it has the same interface as the PIC32 MX i.e. choose which priority uses the SRS.
Can somebody give me a hint about how to use that?
Thanks.

[filip]

Hi,

I apologize for the inconvenience, this feature is currently not supported by the compiler.

I have reported this to our developers, they will address the issue as soon as possible.

Regards,
Filip.

[HiEveryone]

Hi thanks for your reply, I doubted the compiler doesn't support that yet.

What's the behavior of the compiler then when one uses SRS for context switching?
The default value of the PRISS register is 0 which means that all interrupt priorities use the Shodow Register Set 0.
Because the compiler doesn't allow multiple SRS I assume no problem would happen and only interrupt priority 7 uses the Shadow Register Set.
But does changing PRISS changes the SRS that's going to be used ?

Thanks.

[filip]

Hi,

The PRISS register setting should affect the SRS you are using, i.e. if you can set SRSx for priority level set in the code.

Regards,
Filip.