EUSART issue- can't do Full Duplex?

[tgmcn]

Hi,
I'm working with MIDI data which means asynchronous packets of data typically 3bytes long at 31250bps. The following code works fine with a PIC18F4620 running at 32MHz (using PLL mode).

It breaks when the delay line "delay_us(750)" is removed from the while loop. For example rather than:
$90 $30 $40 ... $80 $30 $40 (this is correct)
it puts out:
$90 $20 $00 ... $80 $20 $00

It acts as if usart_write() of bytes #1 and #2 interfere with usart_read() of bytes #2 and #3. Can't the EUSART send and receive at the same time. Datasheet indicates that asynchronous mode is full duplex and this is default. I've tried toggling the CREN bit = but no change. Any Ideas? Thanks,
Tim
- also, has anyone else had the problem of soft_uart_write not working properly at speeds 57600 and above. Using my bitscope I timed the output and 57600 produces an actual bit rate of about 55200, about 5% slow. If I set soft_uart_init to 60088 it produces output at 57600. Yes - I have a frequency counter and my Fosc really is 8.0000 MHz. Is this a known issue in soft_uart?

Code: Select all

program m_rx_tx
'written in MikroBasic 7.0.0.2

symbol M_BUFSIZE = 512

dim dbuf as byte[M_BUFSIZE]  'circular buffer
dim dIN, dOUT as word
dim data as byte

'************************************************************************
'* interrupt **************************************************************
'************************************************************************
sub procedure interrupt
	dim Mdata as byte
	if PIR1.5 = 1 then ' check USART interrupt flag  (pic18)
		Mdata = USART_Read()   ' read the received dat
		dIN = inc(dIN) mod 512
		dbuf[dIN] = Mdata
	end if
end sub

main:
	PIE1.5 = 1    ' RCIE - EUSART receive INT enable.
	INTCON.7 = 1  ' GIE -  Global INT enable
	INTCON.6 = 1  ' PEIE - periph int enable
	'CONFIG1H = $F6  'PLL enable  - set this using Project-Edit
	OSCTUNE.6 = 1   'phase-locked loop enable

	USART_init(31250)
	Soft_Uart_Init(PORTA,3,2,60088,0) 'this actually runs at 57600 baud

	dOUT=0   'output pointer
	dIN = 0  'input pointer

	while TRUE
		if dOUT<>dIN then  'pointer mismatch means new data.
			dOUT = inc(dOUT) mod 512
			data = dbuf[dOUT]   'get next data byte from dbuf

			'with this delay data is perfect
			'without this delay - data is garbled
			delay_us(750)
			'why is the delay necessary?  Can't the EUSART Rx and Tx at the
			'same time?  It's in asynch (FULL DUPLEX) mode.

			USART_write(data)
			soft_uart_write(data)
		end if
	wend
end.